To be held at...STFC Daresbury Laboratory
Wednesday 8 and Thursday 9 July 2009
(With satellite events taking place on Tuesday 7 July)
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| Updated 02/06/09 |
COPIES OF THE SLIDES FROM THIS EVENT ARE NOW AVAILABLE HERE
Registration for the GPU Accelerators Workshop is now CLOSED. We have reached our limit for the number of delegates we can accommodate. Places are still available for Jack Dongarra's seminar on the 7th July - if you would like to attend on the 7th July please email Damian Jones to ensure that your name is passed to security so that you can gain access to the Daresbury site.
(You may also email Damian if you would like to be added to a reserve list for the 8th and 9th July in case we have any cancellations)
We are planning to broadcast the seminars on the 7th July live on the web - more details will follow soon...
WEBCAST - To view a live webcast of the seminars on the 7th July please click here. This link will be available 15 minutes before the start of the seminar.
(STFC employees can watch the broadcast here)
This two day workshop - organised by the Computational Science & Engineering Department at STFC Daresbury Laboratory - offers hands-on training in CUDA and HMPP and requires delegates to bring a laptop running SSH for remote access to local resources (Daresbury GPU cluster).
If you do not have access to a laptop please let us know in advance.
The event will take place on Wednesday 8 and Thursday 9 July and the venue will be...
Tower Seminar Room
Science and Technology Facilities Council
Daresbury Laboratory
Daresbury Science and Innovation Campus
Warrington WA4 4AD
Directions to the Laboratory can be found here and here.
There will also be a series of seminars running as a satellite event to the main workshop on Tuesday 7 July. These will take place in the Merison Lecture Theatre at Daresbury Laboratory and will include seminars by Jack Dongarra, Benoit Raoult and Nvidia. Please see the programme for full details.
BACKGROUND INFORMATION
HMPP
HMPP is a complete hybrid compiler with powerful data-parallel code generators. It includes a C and Fortran compiler, hardware-specific code generators and a runtime that seamlessly integrate in your environment and make use of the hardware vendor development tools and drivers. The code generators are specifically designed to extract the most of data parallelism from C and Fortran kernels and translate them into the language of the targets such as NVIDIA® CUDA™ or SSE.
http://www.caps-entreprise.com/hmpp.html
CUDA
CUDA is a parallel computing architecture developed by NVIDIA. Programmers use 'C for CUDA' (C with NVIDIA extensions) to code algorithms for execution on the GPU. CUDA provides a low and a higher level API, standard libraries, and an interface to Fortran.
http://www.nvidia.com/object/cuda_what_is.html
In addition to that NVIDIA is beta testing OpenCL
http://www.nvidia.com/object/cuda_opencl.html
...and The Portland Group is beta testing its accelerator extensions for its C and Fortran compilers which support CUDA.
http://www.pgroup.com/resources/accel.htm